Power-oriented checkability and monitoring of the current consumption in FPGA projects of the critical applications

Abstract

The article is devoted to the problem of checkability of the circuits as an essential element in ensuring the functional safety of informational and control safety-related systems that monitoring objects of increased risk in the energy, transport, military, space and other industries to prevent accidents and reduce their consequences occurrence. The key role of checkability in the transformation of fault-tolerant structures used in such systems into fail-safe ones is noted. The problems of logical checkability are shown, including the problem of hidden faults, inherent for safety-related systems in the modern design of its components using matrix structures. It was proposed to supplement logical checkability with other forms, among which the most promising are power-oriented checkability, supported by the successful development of green technologies in FPGA (Field Programmable Gate Array) design. The problems of limited accuracy in the assessment and measurement of temperature, which manifested themselves in the development of thermal testability and thermal methods for monitoring circuits, are noted. The lower and upper power-oriented checkability of the circuits is determined by the current consumption parameter. Analytical estimates of the lower and upper checkability of the circuits by current consumption were obtained considering the peculiarities of their design on FPGA using modern CAD (Computer-Aided Design) using the example of Quartus Prime Lite 18.1. The threshold values of consumption currents in the methods of monitoring circuits for detecting faults in the chains of common signals and short-circuit faults within the framework of the lower and upper checkability are estimated, respectively. Experiments have been performed, to evaluate the lower and upper power-oriented checkability of the circuits and threshold values for the presented monitoring methods, using the example of a scalable circuit of the shifting register, designed for FPGA. The dependences of the power-oriented lower and upper checkability of the circuits on the occupancy of the FPGA chip are shown.