Improving FPGA components of critical systems based on natural version redundancy

Abstract

The article is devoted to the problem of improving FPGA (Field Programmable Gate Array) components developed for safety-
related systems. FPGA components are improved in the checkability of their circuits and the trustworthiness of the results calculated

on them to support fault-tolerant solutions, which are basic in ensuring the functional safety of critical systems. Fault-tolerant solu-
tions need protection from sources of multiple failures, which include hidden faults. They can be accumulated in significant quanti-
ties during a long normal operation and disrupt the functionality of fault-tolerant circuits with the onset of the most responsible emer-
gency mode. Protection against hidden faults is ensured by the checkability of the circuits, which is aimed at the manifestation of

faults and therefore must be supported in conjunction with the trustworthiness of the results, taking into account the decrease in
trustworthiness in the event of the manifestation of faults. The problem of increasing the checkability of the FPGA component in

normal operation and the trustworthiness of the results calculated in the emergency mode is solved by using the natural version re-
dundancy inherent in the LUT-oriented architecture (Look-Up Table). This redundancy is manifested in the existence of many ver-
sions of the program code that preserve the functionality of the FPGA component with the same hardware implementation. The

checkability of the FPGA component and the trustworthiness of the calculated results are considered taking into account the typical

failures of the LUT-oriented architecture. These malfunctions are investigated from the standpoint of the consistency of their mani-
festation and masking, respectively, in normal and emergency modes on versions of the program code. Malfunctions are identified

with bit distortion in the memory of the LUT units. Bits that are only observed in emergency mode are potentially dangerous because

they can hide faults in normal mode. Moving potentially dangerous bits to checkable positions, observed in normal mode, is per-
formed by choosing the appropriate versions of the program code and organizing the operation of the FPGA component on several

versions. Experiments carried out with the FPGA component using the example of an iterative array multiplier of binary codes have
shown the effectiveness of using the natural version redundancy of the LUT-oriented architecture to solve the problem of hidden faults.