Analytical modeling of OAM-based programmable hardware accelerators for data-invariant algorithms execution

Abstract

Relevance. The growing demand for high-performance computing in domains such as signal processing and scientific modeling necessitates efficient hardware accelerators capable of predictable and scalable execution of tasks. Algorithms with data-invariant structure, characterized by fixed execution schedules and static data dependencies, represent an important class of workloads that can benefit from specialized architectural solutions. Ordered Access Memory (OAM)-based programmable hardware accelerators offer deterministic and conflict-free parallel data access, making them a promising approach, however, systematic analytical methods for their performance and resource evaluation remain insufficiently developed. Aim and objectives. The aim of the scientific research highlighted in this paper is to develop a unified analytical framework for modeling and evaluation of OAM-based programmable hardware accelerators. The objectives include formalization of memory requirements, computational throughput, and execution time, as well as analysis of architectural trade-offs for different accelerator structures. Methods used. The study employs analytical modeling based on matrix representation of data, instructions, and indices, and derives formal expressions for basic system characteristics as functions of architectural parameters and algorithm properties. A unified execution time model is developed, incorporating preparation, computation, and output phases, with explicit consideration of memory access parallelism and overlapping operations. Comparative analysis is conducted for dual-memory and algorithm-adaptive memory structures. Results. The proposed framework provides models for estimating data, instruction, and index memory requirements, computational throughput, and execution time. It enables systematic exploration of the architectural parameter space and reveals trade-offs between memory organization, degree of parallelism, and performance. The analysis shows that adaptive memory structures reduce redundant data movement, leading to improved execution time and more efficient resource utilization compared to dual-memory designs. Conclusions. The novelty of the work lies in the development of a unified analytical modeling framework that jointly captures memory organization, computational structure, and execution dynamics of OAM-based accelerators. The practical value of the results consists in enabling early-stage, platform-independent evaluation and optimization of accelerator structures for data-invariant algorithms execution, supporting informed design decisions without the need for time-consuming simulation or prototyping.