Improving FPGA components of critical systems based on natural version redundancy

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Oleksandr V. Drozd
Andrzej Rucinski
Kostiantyn V. Zashcholkin
Myroslav O. Drozd
Yulian Yu. Sulima

Abstract

The article is devoted to the problem of improving FPGA (Field Programmable Gate Array) components developed for safety-related systems. FPGA components are improved in the checkability of their circuits and the trustworthiness of the results calculated on them to support fault-tolerant solutions, which are basic in ensuring the functional safety of critical systems. Fault-tolerant solutions need protection from sources of multiple failures, which include hidden faults. They can be accumulated in significant quantities during a long normal operation and disrupt the functionality of fault-tolerant circuits with the onset of the most responsible emergency mode. Protection against hidden faults is ensured by the checkability of the circuits, which is aimed at the manifestation of faults and therefore must be supported in conjunction with the trustworthiness of the results, taking into account the decrease in trustworthiness in the event of the manifestation of faults. The problem of increasing the checkability of the FPGA component in normal operation and the trustworthiness of the results calculated in the emergency mode is solved by using the natural version redundancy inherent in the LUT-oriented architecture (Look-Up Table). This redundancy is manifested in the existence of many versions of the program code that preserve the functionality of the FPGA component with the same hardware implementation. The checkability of the FPGA component and the trustworthiness of the calculated results are considered taking into account the typical failures of the LUT-oriented architecture. These malfunctions are investigated from the standpoint of the consistency of their manifestation and masking, respectively, in normal and emergency modes on versions of the program code. Malfunctions are identified with bit distortion in the memory of the LUT units. Bits that are only observed in emergency mode are potentially dangerous because they can hide faults in normal mode. Moving potentially dangerous bits to checkable positions, observed in normal mode, is performed by choosing the appropriate versions of the program code and organizing the operation of the FPGA component on several versions. Experiments carried out with the FPGA component using the example of an iterative array multiplier of binary codes have shown the effectiveness of using the natural version redundancy of the LUT-oriented architecture to solve the problem of hidden faults.

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Digital control of technical and social systems

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Author Biographies

Oleksandr V. Drozd, Odessa National Polytechnic University, 1, Shevchenko Avenue. Odesa, 65044, Ukraine

Dr. Sci. (Eng.) (2003), Prof. of Computer Intellectual Systems and Networks Department

Andrzej Rucinski, Hampshire, Durham, New Hampshire 03824. Boston, USA

PhD Professor Emeritus, Department of Electrical and Computer Engineering, University of New
Hampshire, a member of the Executive Committee (Innovation Chair) of the IEEE Computer Society’s Design Automation Technical Committee. USA Ambassador of International Society of Service Innovation Professionals. University of New

Kostiantyn V. Zashcholkin, Odessa National Polytechnic University, 1, Shevchenko Avenue. Odessa, 65044, Ukraine

Dr. Sci. (Eng) (2020), Associate Professor of the Department of Computer Intelligent Systems and Networks

Myroslav O. Drozd, Odessa National Polytechnic University, 1, Shevchenko Avenue. Odessa, 65044, Ukraine

PhD (2014), Associated Prof. of Information Systems Department

Yulian Yu. Sulima, SSU “Odessa Technical Professional College of the Odessa National Academy of Food Technology”, 54, Balkivska St. Odessa, 65006, Ukraine

PhD (2014), Head of the Computer Systems Department

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