Image buffering in application specific processors

Abstract

In many digital image-processing applications, which are implemented in field programmable gate arrays, the currently
processed image's frames are stored in external dynamic memory. The performance of such an application depends on the dynamic
memory speed and the necessary requests quantity during algorithm’s runtime. This performance is being optimized through field
programmable gate arrays - implemented buffer memory usage. But there is no common method for the formal buffer memory
synthesis with preset throughput, input and output data sequence order and minimized hardware costs. In this article, the features of
image input and processing based on Field Programmable Gate Array are considered. The methods of building buffer circuits in field
programmable gate arrays, due to which the intensity of data exchanges with external memory is reduced, are analyzed. The method
of synthesizing pipeline circuits with specified performance characteristics and the data sequence order is given, which is based on
the mapping of the spatial synchronous data flows into the structure implemented in the field programmable gate arrays. A method of
designing buffer schemes is proposed, which is based on the mapping of spatial synchronous data flows into local memory in the
form of chains of pipeline registers. The method helps to organize the data flow of at the input of built-in pipeline units of image
processing, in which the data follow in a given order, and to minimize the amount of buffer memory. The method ensures the use of
dynamically adjustable register delays built into the field programmable gate arrays, which increases the efficiency of buffering. This
method was tested during the development of an intelligent video camera. The embedded hardware implements a video image
compression algorithm with a wide dynamic range according to the Retinex algorithm. The same time it selects characteristic points
in the image for the further pattern recognition. At the same time, multiple decimation of the frame is performed. Due to the multirate
buffering of the image in the field programmable gate arrays, it was possible to avoid using of external dynamic memory.